ERR_INTERRUPT=Val_0x0, CARD_REMOVAL=Val_0x0, CARD_INTERRUPT=Val_0x0, BUF_RD_READY=Val_0x0, BGAP_EVENT=Val_0x0, CMD_COMPLETE=Val_0x0, BUF_WR_READY=Val_0x0, FX_EVENT=Val_0x0, CARD_INSERTION=Val_0x0, DMA_INTERRUPT=Val_0x0, XFER_COMPLETE=Val_0x0
Normal Interrupt Status Register
| CMD_COMPLETE | Command Complete. In both SD and eMMC modes, this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. This interrupt is not generated when the SDMMC_XFER_MODE_R[RESP_INT_DISABLE] bit is set to 0x1. 0 (Val_0x0): No command complete 1 (Val_0x1): Command complete. Write 0x1 to clear. |
| XFER_COMPLETE | Transfer Complete. This bit is set when a read and write transfer and a command with status busy is completed. 0 (Val_0x0): Not complete 1 (Val_0x1): Command execution is completed. Write 0x1 to clear. |
| BGAP_EVENT | Block Gap Event. This bit is set when both read and write transaction is stopped at block gap due to a Stop at Block Gap Request (SDMMC_BGAP_CTRL_R[STOP_BG_REQ]). 0 (Val_0x0): No block gap event 1 (Val_0x1): Transaction stopped at block gap. Write 0x1 to clear. |
| DMA_INTERRUPT | DMA Interrupt. This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer (refer to SDMMC_BLOCKSIZE_R). In case of ADMA, by setting the Interrupt field in the descriptor table, the Host Controller generates this interrupt. This interrupt is not generated after a Transfer Complete. 0 (Val_0x0): No DMA interrupt 1 (Val_0x1): DMA Interrupt is generated. Write 0x1 to clear. |
| BUF_WR_READY | Buffer Write Ready. This bit is set if the SDMMC_PSTATE_REG[BUF_WR_ENABLE] bit changes from 0x0 to 0x1. 0 (Val_0x0): Not ready to write buffer 1 (Val_0x1): Ready to write buffer. Write 0x1 to clear. |
| BUF_RD_READY | Buffer Read Ready. This bit is set if the SDMMC_PSTATE_REG[BUF_RD_ENABLE] bit changes from 0x0 to 0x1. 0 (Val_0x0): Not ready to read buffer 1 (Val_0x1): Ready to read buffer. Write 0x1 to clear. |
| CARD_INSERTION | Card Insertion. This bit is set if the Card Inserted in the Present State register changes from 0x0 to 0x1. 0 (Val_0x0): Card state stable or debouncing 1 (Val_0x1): Card inserted. Write 0x1 to clear. |
| CARD_REMOVAL | Card Removal. This bit is set if the Card Inserted in the Present State register changes from 0x1 to 0x0. 0 (Val_0x0): Card state stable or debouncing 1 (Val_0x1): Card removed. Write 0x1 to clear. |
| CARD_INTERRUPT | Card Interrupt. This bit reflects the synchronized value of DAT[1] Interrupt input for SD mode 0 (Val_0x0): No card interrupt 1 (Val_0x1): Generate card Interrupt |
| INT_A | INT_A (Embedded). This bit is set if INT_A is enabled. |
| INT_B | INT_B (Embedded). This bit is set if INT_B is enabled. |
| INT_C | INT_C (Embedded). This bit is set if INT_C is enabled. |
| FX_EVENT | FX Event. This status is set when R[14] of response register is set to 0x1 and Response Type R1/R5 is set to 0x0 in the SDMMC_XFER_MODE_R register. This interrupt is used with response check function. 0 (Val_0x0): No event 1 (Val_0x1): FX Event is detected |
| ERR_INTERRUPT | Error Interrupt. If any of the operating bits in the SDMMC_ERROR_INT_STAT_R register are set, then this bit is set. 0 (Val_0x0): No error 1 (Val_0x1): Error |